 Publications
A 3rd -Order 9-Bit 10-MHz CMOS ΔΣ Modulator with One Active Stage
Abstract—We present a wideband architecture for ΔΣ
modulators using a single active stage and two switched capacitor
passive stages. The mixed active-passive implementation has
performance advantages over traditional Switched Capacitor
(SC) or Continuous Time implementations, particularly for high
resolution, wideband applications with high sampling rates and
moderate oversampling ratios. Design insensitivity to clock jitter
and process variations is achieved by the good choice of the
modulator architecture. The proposed modulator is designed in
0.13-μm CMOS technology and meets all major requirements for
application in IEEE 802.16 wireless MAN receivers. Circuit
simulations show that the modulator with a single bit quantizer
consumes 5.5 mW from a 1.2 V power supply and achieves a 9-b
resolution over a 10-MHz bandwidth at an OSR of 32. Good
performance is also achieved for lower bandwidth applications.
Index Terms—ADC, Delta Sigma, Passive, Switched-Capacitor, Wideband, Receiver.
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